Digital Logic Design

From logic gates to FSMs and Verilog—understand how 1s and 0s drive complex hardware decisions. Digital logic is the foundation of all digital electronics, from simple flip-flops to modern processors.

[Diagram: Digital system with combinational and sequential logic blocks]

Logic Gates

Logic gates are the fundamental building blocks of digital circuits. They perform basic boolean operations on binary inputs.

Basic Gates

AND OR NOT NAND NOR XOR XNOR

AND Gate Truth Table

A	B	A AND B
0	0	0
0	1	0
1	0	0
1	1	1

XOR Gate Truth Table

A	B	A XOR B
0	0	0
0	1	1
1	0	1
1	1	0

💡 Universal Gates: NAND and NOR gates are called "universal gates" because any logic function can be implemented using only NAND gates (or only NOR gates)!

Boolean Algebra

Boolean algebra provides the mathematical foundation for analyzing and simplifying digital circuits.

Key Laws

Identity: A + 0 = A, A · 1 = A
Null: A + 1 = 1, A · 0 = 0
Complement: A + A' = 1, A · A' = 0
De Morgan's: (A · B)' = A' + B', (A + B)' = A' · B'
Distributive: A · (B + C) = A·B + A·C

Simplification Example

          // Original expression F = A'BC + AB'C + ABC' + ABC // Factor out
          common terms F = A'BC + AB'C + AB(C' + C) F = A'BC + AB'C + AB // This
          is the simplified Sum-of-Products form // Can be further simplified
          using K-maps
        

Combinational Logic

Combinational circuits have outputs that depend only on current inputs—no memory or feedback.

Common Combinational Circuits

Multiplexer (MUX): Selects one of many inputs based on select lines
Demultiplexer (DEMUX): Routes one input to one of many outputs
Decoder: Converts binary code to one-hot encoding
Encoder: Converts one-hot to binary code
Adder: Half-adder, Full-adder, Ripple-carry adder
Comparator: Compares two binary numbers

[Diagram: 4-to-1 Multiplexer with select lines S1, S0]

Sequential Logic

Sequential circuits have memory—outputs depend on both current inputs and past states.

Flip-Flops

SR Flip-Flop: Set-Reset, basic memory element
D Flip-Flop: Data/Delay, captures input on clock edge
JK Flip-Flop: No invalid state, toggle capability
T Flip-Flop: Toggle mode, useful for counters

D Flip-Flop in Verilog

          // Positive-edge triggered D Flip-Flop with reset module d_ff ( input
          wire clk, input wire rst_n, // Active-low reset input wire d, output
          reg q ); always @(posedge clk or negedge rst_n) begin if (!rst_n) q <=
          1'b0; else q <= d; end endmodule
        

Finite State Machines (FSM)

FSMs model systems that transition between a finite number of states based on inputs. They're essential for control logic, protocol handling, and sequential behavior.

FSM Types

Mealy Machine: Outputs depend on current state AND inputs
Moore Machine: Outputs depend only on current state

[Diagram: State diagram for a traffic light controller]

FSM Example: Traffic Light Controller

          // Traffic Light FSM in Verilog module traffic_light ( input wire clk,
          input wire rst_n, output reg [2:0] light // {Red, Yellow, Green} ); //
          State encoding localparam S_GREEN = 2'b00; localparam S_YELLOW =
          2'b01; localparam S_RED = 2'b10; reg [1:0] state, next_state; reg
          [3:0] counter; // State register always @(posedge clk or negedge
          rst_n) begin if (!rst_n) state <= S_RED; else state <= next_state; end
          // Next state logic always @(*) begin case (state) S_GREEN: next_state
          = (counter == 10) ? S_YELLOW : S_GREEN; S_YELLOW: next_state =
          (counter == 3) ? S_RED : S_YELLOW; S_RED: next_state = (counter == 10)
          ? S_GREEN : S_RED; default: next_state = S_RED; endcase end // Output
          logic (Moore - depends only on state) always @(*) begin case (state)
          S_GREEN: light = 3'b001; // Green on S_YELLOW: light = 3'b010; //
          Yellow on S_RED: light = 3'b100; // Red on default: light = 3'b100;
          endcase end endmodule
        

Introduction to Verilog

Verilog is a Hardware Description Language (HDL) used to model, simulate, and synthesize digital circuits.

Verilog Basics

          // Module definition module my_module ( input wire [7:0] data_in,
          input wire enable, output reg [7:0] data_out ); // Combinational logic
          using assign wire [7:0] inverted = ~data_in; // Sequential logic using
          always block always @(posedge clk) begin if (enable) data_out <=
          data_in; end endmodule
        

Key Verilog Concepts

wire: Continuous assignment, combinational connections
reg: Procedural assignment, can hold state
assign: Continuous (combinational) assignment
always @(*): Combinational logic block
always @(posedge clk): Sequential logic block
Blocking (=) vs Non-blocking (<=): Use = for combinational, <= for sequential

4-bit Counter in Verilog

          module counter_4bit ( input wire clk, input wire rst_n, input wire
          enable, output reg [3:0] count ); always @(posedge clk or negedge
          rst_n) begin if (!rst_n) count <= 4'b0000; else if (enable) count <=
          count + 1; end endmodule
        

Timing Concepts

Setup Time: Data must be stable before clock edge
Hold Time: Data must remain stable after clock edge
Propagation Delay: Time for signal to travel through a gate
Clock-to-Q Delay: Time from clock edge to output change
Critical Path: Longest combinational path, determines max frequency

⚡ Timing Violation: If setup or hold times are violated, the flip-flop may enter a metastable state, leading to unpredictable behavior!

FPGA Implementation

FPGAs (Field-Programmable Gate Arrays) allow you to implement custom digital logic in hardware:

LUTs (Look-Up Tables): Implement combinational logic
Flip-Flops: Implement sequential logic
Block RAM: On-chip memory
DSP Blocks: Optimized for math operations
I/O Blocks: Interface with external pins

Popular FPGA development boards:

Xilinx Artix-7 Intel Cyclone V Lattice iCE40 Gowin GW1N

🎯 Key Takeaway: Digital logic design bridges the gap between software concepts and physical hardware. Master gates, flip-flops, FSMs, and Verilog to design custom digital systems from scratch!