2:1 Multiplexer
Design a simple 2:1 multiplexer in Verilog.
Constraints
- sel=0 => a
- sel=1 => b
- combinational only
- assign statement allowed
1module mux2(2 input wire a,3 input wire b,4 input wire sel,5 output wire y6);7// TODO8endmodule
Design a simple 2:1 multiplexer in Verilog.
1module mux2(2 input wire a,3 input wire b,4 input wire sel,5 output wire y6);7// TODO8endmodule