DeetCode.

AND/OR Combinational Block

Easy Verilog FSM
Solve this problem

Design a combinational logic block in Verilog that outputs AND and OR of two 1-bit inputs a and b.

Constraints

  • Purely combinational.
  • Use continuous assignment.
  • Inputs 1-bit.
  • Outputs 1-bit.
Starter codeVerilog
1module and_or(2    input wire a,3    input wire b,4    output wire and_out,5    output wire or_out6);7// TODO8endmodule