DeetCode.

Assertion-Based Protocol Checker

Hard Verilog Verification Asked at Cadence
Solve this problem

Write a checker module with SystemVerilog assertions that verifies a simple request/acknowledge handshake, catching protocol violations during simulation.

Constraints

  • req must stay high until ack is seen.
  • ack must never be asserted without a pending req.
  • ack must arrive within 16 cycles of req.
  • Each rule is its own named assertion.
  • Assertions must be disabled during reset.
  • No changes to the design under test.
Starter codeVerilog
1module handshake_checker (2    input wire clk,3    input wire rst,4    input wire req,5    input wire ack6);7// TODO: assertions8endmodule