Async FIFO Pointer Logic

Hard VHDL Synchronization Asked at Xilinx

Implement the Gray-coded pointer and synchroniser logic for an asynchronous FIFO, which is the part that actually makes a dual-clock FIFO safe.

Constraints

Write and read pointers are one bit wider than the address.
Pointers cross clock domains as Gray code through two flops.
Full is detected by comparing the top two bits inverted.
Empty is a plain equality on the synchronised pointer.
No combinational path between the two clock domains.
Depth is a power of two.

Starter codeVHDL

1library ieee;2use ieee.std_logic_1164.all;3use ieee.numeric_std.all;4 5entity async_fifo_ptr is6    generic ( AW : positive := 4 );7    port (8        wclk, wrst, w_en : in  std_logic;9        rclk, rrst, r_en : in  std_logic;10        full  : out std_logic;11        empty : out std_logic12    );13end async_fifo_ptr;