DeetCode.

AXI-lite Register Bank

Hard Verilog Protocols
Solve this problem

Design an AXI-Lite register bank in Verilog that supports 4 32-bit registers. The module must handle read/write transactions, assert ready/valid appropriately, and avoid bus contention. Registers must be memory-mapped at offsets 0x0, 0x4, 0x8, and 0xC.

Constraints

  • 4 registers, 32-bit each.
  • AXI-lite slave interface.
  • Support read and write operations.
  • Generate read_data and ready signals.
  • Synchronous reset.
  • No burst transactions.
Starter codeVerilog
1module axi_reg(2    input wire clk,3    input wire rst,4    input wire [3:0] awaddr,5    input wire wvalid,6    input wire [31:0] wdata,7    input wire [3:0] araddr,8    input wire rvalid,9    output reg [31:0] rdata10);11// TODO12endmodule