DeetCode.

Carry-Save Adder Stage

Hard Verilog Architecture Asked at NVIDIA
Solve this problem

Implement a 3-to-2 carry-save adder stage, the building block that lets a multiplier sum many partial products without a carry ripple at every level.

Constraints

  • Three 8-bit inputs, two 8-bit outputs (sum and carry).
  • Purely combinational, no clock.
  • The carry output is shifted left by one.
  • Must have no carry propagation between bit positions.
  • Use a generate loop over full adders.
  • Verify that sum + carry equals a + b + c.
Starter codeVerilog
1module csa_stage (2    input wire [7:0] a,3    input wire [7:0] b,4    input wire [7:0] c,5    output wire [7:0] sum,6    output wire [8:0] carry7);8// TODO9endmodule