CDC Synchronizer

Hard Verilog Concurrency

Implement a 2-stage synchronizer for crossing asynchronous clock domains in Verilog. The synchronizer must reduce metastability and produce a stable output in destination clock domain.

Constraints

2 flip-flop stages.
async_in sampled into destination domain.
Rising edge triggered.
Synchronous reset.
Output stable value.

Starter codeVerilog

1module cdc(2    input wire clk,3    input wire rst,4    input wire async_in,5    output reg sync_out6);7// TODO8endmodule