DeetCode.

Clock Divider

Medium Verilog FSM
Solve this problem

Design a clock divider in Verilog that divides the input clock by an integer factor. The divider must use a counter and produce a 50% duty cycle output when possible.

Constraints

  • Parameter DIV sets divide factor.
  • Input clk, output clk_out.
  • Synchronous reset.
  • Use counter wrapping at DIV-1.
Starter codeVerilog
1module clk_div(2    input wire clk,3    input wire rst,4    output reg clk_out5);6parameter DIV = 4;7// TODO8endmodule