DeetCode.

Clock Enable Generator

Easy VHDL Timing Asked at STMicroelectronics
Solve this problem

Generate a single-cycle clock enable pulse at a divided rate, which is the correct way to run slower logic without creating a second clock domain.

Constraints

  • Division factor is a generic.
  • Output is a one-cycle-wide pulse, not a divided clock.
  • Pulse rate is the input clock divided by the generic.
  • Synchronous reset clears the counter and output.
  • Counter width derived from the generic.
  • Must not generate a gated clock.
Starter codeVHDL
1library ieee;2use ieee.std_logic_1164.all;3use ieee.numeric_std.all;4 5entity clk_enable is6    generic ( DIVIDE : positive := 100 );7    port (8        clk : in  std_logic;9        rst : in  std_logic;10        ce  : out std_logic11    );12end clk_enable;