DeetCode.

Clock Gating Cell

Medium Verilog Power Asked at MediaTek
Solve this problem

Implement a glitch-free integrated clock gating cell using a latch, so enabling and disabling a clock branch never produces a runt pulse.

Constraints

  • Use a low-transparent latch on the enable.
  • The gated clock is the latched enable ANDed with the clock.
  • Enable changes must only take effect while the clock is low.
  • Include a test-enable input that forces the clock through.
  • No flip-flop on the enable path - it must be a latch.
  • Must not produce a partial clock pulse under any enable timing.
Starter codeVerilog
1module clock_gate (2    input wire clk,3    input wire enable,4    input wire test_enable,5    output wire gated_clk6);7// TODO8endmodule