Comparator Block

Medium VHDL FSM

Design a VHDL comparator module that compares two unsigned 8-bit inputs and asserts gt, lt, or eq flags accordingly.

Constraints

a,b unsigned(7 downto 0).
gt='1' if a>b.
lt='1' if a<b.
eq='1' if a=b.
Synchronous reset clears outputs.

Starter codeVHDL

1entity comp is2  Port ( clk: in std_logic;3         rst: in std_logic;4         a: in unsigned(7 downto 0);5         b: in unsigned(7 downto 0);6         gt: out std_logic;7         lt: out std_logic;8         eq: out std_logic);9end comp;