DeetCode.

Counter with Enable

Medium Verilog FSM
Solve this problem

Implement a counter in Verilog that increments only when enable is asserted. Include synchronous reset and parameterized width.

Constraints

  • Parameter WIDTH.
  • Count wraps around.
  • Enable gates count.
  • Reset clears count.
  • Rising edge triggered.
Starter codeVerilog
1module counter(2    input wire clk,3    input wire rst,4    input wire en,5    output reg [7:0] count6);7// TODO8endmodule