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D Flip-Flop Process

Easy VHDL FSM
Solve this problem

Write a VHDL process for a single-bit D flip-flop with synchronous active-high reset.

Constraints

  • Reset forces q='0'.
  • Rising edge triggered.
  • q follows d.
Starter codeVHDL
1entity dff is2  Port ( clk: in std_logic;3         rst: in std_logic;4         d: in std_logic;5         q: out std_logic);6end dff;