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D Flip-Flop with Reset

Easy Verilog FSM
Solve this problem

Design a D flip-flop in Verilog with synchronous active-high reset. The flip-flop must output q on rising clock edges.

Constraints

  • Reset clears q to 0.
  • Trigger on rising clock edge only.
  • Ignore D changes during reset.
  • Output port name: q.
Starter codeVerilog
1module dff(2    input wire clk,3    input wire rst,4    input wire d,5    output reg q6);7 8// TODO9 10endmodule