DeetCode.

Debouncer with Counter

Medium Verilog Robustness Asked at Garmin
Solve this problem

Implement a hardware debouncer that only propagates an input change after it has been stable for a parameterised number of clock cycles.

Constraints

  • Stability window is a parameter, default 1000 cycles.
  • Output changes only after the window elapses.
  • Any change in the raw input restarts the counter.
  • Include a two-flop synchroniser on the raw input first.
  • Synchronous reset sets the output low.
  • Counter width derived from the parameter.
Starter codeVerilog
1module debouncer #(parameter STABLE = 1000) (2    input wire clk,3    input wire rst,4    input wire noisy,5    output reg clean6);7// TODO8endmodule