DeetCode.

Delay Line with Generic Depth

Medium VHDL Configuration Asked at Analog Devices
Solve this problem

Build a configurable delay line that holds a data word for N clock cycles, used to align a data path against a slower control path.

Constraints

  • Width and depth are generics.
  • Depth of 0 must pass the input straight through combinationally.
  • Depth of 1 or more inserts that many register stages.
  • Include a clock enable.
  • Synchronous reset clears every stage.
  • Use a generate statement to build the chain.
Starter codeVHDL
1library ieee;2use ieee.std_logic_1164.all;3 4entity delay_line is5    generic ( WIDTH : positive := 8; DEPTH : natural := 3 );6    port (7        clk : in  std_logic;8        rst : in  std_logic;9        ce  : in  std_logic;10        din : in  std_logic_vector(WIDTH-1 downto 0);11        dout: out std_logic_vector(WIDTH-1 downto 0)12    );13end delay_line;