Detect Metastability Window

Hard Verilog Determinism Asked at Intel
Solve this problem

Write a testbench that measures the setup and hold window of a flip-flop model by sweeping the data edge across the clock edge and detecting when the output becomes unknown.

Constraints

  • Sweep the data transition in 1 ps steps across the clock edge.
  • Detect an X or an unexpected value on q.
  • Report the first and last failing offsets.
  • Use timescale 1ps/1ps.
  • Must not rely on a fixed delay guess.
  • Print the measured window width.
Starter codeVerilog
1`timescale 1ps/1ps2 3module metastability_tb;4// TODO5endmodule