Digital PLL Loop Filter
Design and simulate a second-order digital PLL loop filter, and verify that the loop locks to a frequency step within the expected settling time.
Constraints
- Proportional-plus-integral loop filter.
- Compute the coefficients from a target loop bandwidth and damping factor.
- Simulate the phase error response to a frequency step.
- Report the settling time to within 5 percent.
- The loop must be stable for a damping factor of 0.707.
- Fixed timestep simulation.
1function result = pll_lock(bw_hz, zeta, fs, freq_step_hz)2% TODO3end