DeetCode.

Dual-Port RAM

Medium Verilog Memory Asked at Xilinx
Solve this problem

Infer a true dual-port RAM with independent read and write ports on separate clocks, the way a synthesis tool expects so it maps to a block RAM primitive.

Constraints

  • Parameterised width and depth.
  • Port A is write-first, port B is read-only.
  • Both ports have their own clock.
  • Reads are registered (one cycle of latency).
  • Must infer block RAM, so no reset on the memory array.
  • No initial block.
Starter codeVerilog
1module dual_port_ram #(2    parameter WIDTH = 8,3    parameter DEPTH = 2564)(5    input wire clk_a,6    input wire we_a,7    input wire [$clog2(DEPTH)-1:0] addr_a,8    input wire [WIDTH-1:0] din_a,9    output reg [WIDTH-1:0] dout_a,10    input wire clk_b,11    input wire [$clog2(DEPTH)-1:0] addr_b,12    output reg [WIDTH-1:0] dout_b13);14// TODO15endmodule