DeetCode.

Edge Detector

Easy Verilog Timing Asked at Samsung
Solve this problem

Build a module that produces single-cycle pulses on the rising edge, the falling edge and either edge of a synchronous input signal.

Constraints

  • Three outputs: rise, fall and both.
  • Each pulse is exactly one clock cycle.
  • No pulse in the cycle immediately after reset.
  • Input is already synchronous to clk.
  • Use a single delay register.
Starter codeVerilog
1module edge_detect (2    input wire clk,3    input wire rst,4    input wire signal,5    output wire rise,6    output wire fall,7    output wire both8);9// TODO10endmodule