DeetCode.

FIFO with Flags

Hard VHDL Memory
Solve this problem

Design a synchronous FIFO with status flags in VHDL. The FIFO must support push/pop and expose full, empty, and almost_full flags. Depth is 16 entries.

Constraints

  • Data width = 8 bits.
  • FIFO depth = 16.
  • full when count=16.
  • empty when count=0.
  • almost_full when count>=14.
  • Synchronous reset.
  • Registers: read_ptr, write_ptr, count.
  • Blocking push on full.
  • Blocking pop on empty.
Starter codeVHDL
1entity fifo16 is2  Port ( clk: in std_logic;3         rst: in std_logic;4         push: in std_logic;5         pop: in std_logic;6         din: in std_logic_vector(7 downto 0);7         dout: out std_logic_vector(7 downto 0);8         full: out std_logic;9         empty: out std_logic;10         almost_full: out std_logic);11end fifo16;