DeetCode.

FSM Traffic Controller

Medium Verilog FSM
Solve this problem

Implement a traffic light FSM with states RED, GREEN, YELLOW.

Constraints

  • Synchronous.
  • Reset->RED.
  • Sequence RED->GREEN->YELLOW->RED.
Starter codeVerilog
1module traffic(2    input wire clk,3    input wire rst,4    output reg [1:0] light5);6// TODO7endmodule