DeetCode.

Gray Code Counter for CDC

Medium Verilog Synchronization Asked at Intel
Solve this problem

Build a Gray-coded binary counter for use as an asynchronous FIFO pointer. Only one bit may change per increment so a synchroniser can never sample a corrupt value.

Constraints

  • 4-bit counter with an enable.
  • Output both the binary and the Gray-coded value.
  • Exactly one Gray output bit changes per increment.
  • Synchronous reset to zero.
  • The Gray conversion must be combinational from the binary register.
  • No blocking assignments in the sequential block.
Starter codeVerilog
1module gray_counter (2    input wire clk,3    input wire rst,4    input wire enable,5    output reg  [3:0] binary,6    output wire [3:0] gray7);8// TODO9endmodule