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Johnson Counter

Easy Verilog FSM Asked at Lattice Semiconductor
Solve this problem

Design a 4-bit Johnson (twisted ring) counter in Verilog. The inverted MSB feeds back into the LSB, giving 8 unique states from 4 flip-flops.

Constraints

  • 4-bit output register q.
  • Synchronous active-high reset clears q to 0.
  • On each rising clock edge, shift left and feed ~q[3] into q[0].
  • Sequence must be 0000, 0001, 0011, 0111, 1111, 1110, 1100, 1000, then repeat.
  • No blocking assignments in sequential logic.
Starter codeVerilog
1module johnson_counter (2    input wire clk,3    input wire rst,4    output reg [3:0] q5);6// TODO7endmodule