DeetCode.

LFSR Pseudo-Random Generator

Medium Verilog Security Asked at Synopsys
Solve this problem

Implement a maximal-length 16-bit linear feedback shift register for built-in self test, producing 65535 states before repeating.

Constraints

  • Fibonacci LFSR with taps at 16, 14, 13 and 11.
  • Seed must be loadable and must never be all zeros.
  • A zero seed must be replaced with a non-zero default.
  • One shift per clock when enabled.
  • Output the full 16-bit state.
  • Period must be 65535.
Starter codeVerilog
1module lfsr16 (2    input wire clk,3    input wire rst,4    input wire enable,5    input wire load,6    input wire [15:0] seed,7    output reg [15:0] state8);9// TODO10endmodule