DeetCode.

Moore FSM Sequence Detector

Medium VHDL FSM Asked at Bosch
Solve this problem

Design a Moore machine that detects the overlapping bit sequence 1011 in a serial input stream and pulses its output for one cycle on each detection.

Constraints

  • Overlapping matches must be detected, so 1011011 gives two hits.
  • Moore output: it depends only on the state.
  • Five states including the idle state.
  • Synchronous reset to idle.
  • Two-process style with separate state register and next-state logic.
  • Output must be registered by construction, not by an extra flop.
Starter codeVHDL
1library ieee;2use ieee.std_logic_1164.all;3 4entity seq_detect is5    port (6        clk  : in  std_logic;7        rst  : in  std_logic;8        din  : in  std_logic;9        hit  : out std_logic10    );11end seq_detect;