DeetCode.

Parameterized Timer

Hard VHDL FSM
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Implement a parameterized countdown timer in VHDL.

Constraints

  • Generic WIDTH defines counter size.
  • Active-high synchronous reset.
  • Count down to zero.
  • Output tick asserted for 1 cycle on zero.
Starter codeVHDL
1entity timer is2  generic ( WIDTH : integer := 8 );3  Port ( clk: in std_logic;4         rst: in std_logic;5         start: in std_logic;6         tick: out std_logic);7end timer;