DeetCode.

Parity Generator and Checker

Easy Verilog Validation Asked at Broadcom
Solve this problem

Build a combinational even-parity generator for an 8-bit word and a matching checker that flags a single-bit error in the received 9-bit frame.

Constraints

  • Generator outputs one parity bit for even parity.
  • Checker takes 8 data bits plus the received parity and outputs an error flag.
  • Purely combinational.
  • Use a reduction XOR, not a loop.
  • Error must be high when the parity does not match.
Starter codeVerilog
1module parity_gen (2    input wire [7:0] data,3    output wire parity4);5endmodule6 7module parity_check (8    input wire [7:0] data,9    input wire parity_in,10    output wire error11);12endmodule