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Pipelined Adder

Hard Verilog Architecture
Solve this problem

Design a 2-stage pipelined 16-bit adder in Verilog. Stage 1 performs partial addition, and Stage 2 produces the final result. The goal is to improve timing on high-frequency datapaths.

Constraints

  • Inputs a and b are 16-bit.
  • Output sum is 16-bit.
  • Pipeline register between stage1 and stage2.
  • Include synchronous reset.
  • Register inputs and outputs.
  • Latency = 2 cycles.
Starter codeVerilog
1module pipe_adder(2    input wire clk,3    input wire rst,4    input wire [15:0] a,5    input wire [15:0] b,6    output reg [15:0] sum7);8// TODO9endmodule