DeetCode.

Pipelined FIFO

Hard Verilog Memory
Solve this problem

Design a pipelined FIFO in Verilog with separate push and pop stages and valid-ready handshaking. Must include registers for input and output stages, depth of 16, and full/empty flags.

Constraints

  • 16 entries, 8-bit.
  • ready/valid signals.
  • separate input/output pipelines.
  • synchronous reset.
  • detect full/empty.
Starter codeVerilog
1module fifo_piped(2    input wire clk,3    input wire rst,4    input wire push,5    input wire [7:0] din,6    input wire pop,7    output reg [7:0] dout8);9// TODO10endmodule