DeetCode.

Pipelined Register Bank

Hard Verilog Architecture
Solve this problem

Design a pipelined register bank in Verilog with read-after-write forwarding. It must contain 8 32-bit registers, support synchronous write and asynchronous read, and include a forwarding path to avoid hazards.

Constraints

  • 8 registers, 32-bit.
  • read1/read2 ports asynchronous.
  • write synchronous.
  • forwarding: if read matches write reg in same cycle, return write data.
  • Reset clears registers.
Starter codeVerilog
1module regbank(2    input wire clk,3    input wire rst,4    input wire we,5    input wire [2:0] waddr,6    input wire [31:0] wdata,7    input wire [2:0] raddr1,8    input wire [2:0] raddr2,9    output reg [31:0] rdata1,10    output reg [31:0] rdata211);12// TODO13endmodule