DeetCode.

Pulse Stretcher

Easy Verilog Timing Asked at Micron
Solve this problem

Stretch a single-cycle input pulse into an output pulse that stays high for a parameterised number of clock cycles, so a slow consumer cannot miss it.

Constraints

  • Stretch length is a module parameter, default 16.
  • A new input pulse during the stretch restarts the count.
  • Output must return low exactly after the programmed length.
  • Synchronous reset clears the output.
  • Counter must not be wider than needed.
Starter codeVerilog
1module pulse_stretch #(parameter LENGTH = 16) (2    input wire clk,3    input wire rst,4    input wire pulse_in,5    output reg pulse_out6);7// TODO8endmodule