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PWM Module

Medium VHDL Control
Solve this problem

Design a PWM generator in VHDL with configurable duty cycle. The PWM must run with an 8-bit counter and produce output HIGH for duty counts and LOW otherwise.

Constraints

  • duty: 8 bits.
  • Counter wraps at 255.
  • pwm='1' when cnt < duty.
  • synchronous reset.
Starter codeVHDL
1entity pwm is2  Port ( clk: in std_logic;3         rst: in std_logic;4         duty: in unsigned(7 downto 0);5         pwm: out std_logic);6end pwm;