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PWM with Configurable Resolution

Medium VHDL Control Asked at Infineon
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Generate a PWM signal whose resolution and frequency are set by generics, with a duty cycle that can be updated safely while the output is running.

Constraints

  • Resolution in bits is a generic.
  • Duty updates take effect only at the start of a period.
  • 0 duty gives a permanently low output, maximum duty gives permanently high.
  • Synchronous reset.
  • No glitches when the duty changes mid-period.
  • Use numeric_std.
Starter codeVHDL
1library ieee;2use ieee.std_logic_1164.all;3use ieee.numeric_std.all;4 5entity pwm is6    generic ( RESOLUTION : positive := 8 );7    port (8        clk  : in  std_logic;9        rst  : in  std_logic;10        duty : in  std_logic_vector(RESOLUTION-1 downto 0);11        pwm_out : out std_logic12    );13end pwm;