Register File with Two Read Ports

Medium VHDL Architecture Asked at ARM

Implement a 16-entry by 32-bit register file with two asynchronous read ports and one synchronous write port, as a simple RISC datapath needs.

Constraints

Register 0 always reads as zero and ignores writes.
Two independent read addresses, combinational reads.
One write port, synchronous, with a write enable.
A read of the address being written must return the old value.
Use numeric_std.
No reset on the array itself.

Starter codeVHDL

1library ieee;2use ieee.std_logic_1164.all;3use ieee.numeric_std.all;4 5entity regfile is6    port (7        clk    : in  std_logic;8        we     : in  std_logic;9        waddr  : in  std_logic_vector(3 downto 0);10        wdata  : in  std_logic_vector(31 downto 0);11        raddr1 : in  std_logic_vector(3 downto 0);12        raddr2 : in  std_logic_vector(3 downto 0);13        rdata1 : out std_logic_vector(31 downto 0);14        rdata2 : out std_logic_vector(31 downto 0)15    );16end regfile;