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Register with Reset

Easy VHDL FSM
Solve this problem

Implement a single-bit register in VHDL with synchronous active-high reset.

Constraints

  • Rising edge clock.
  • reset forces q='0'.
  • q follows d otherwise.
Starter codeVHDL
1entity reg1 is2  Port ( clk: in std_logic;3         rst: in std_logic;4         d: in std_logic;5         q: out std_logic);6end reg1;