DeetCode.

Reset Synchronizer

Medium Verilog Initialization Asked at Intel
Solve this problem

Build an asynchronous-assert, synchronous-deassert reset synchroniser so a reset release never violates recovery time on the flops it feeds.

Constraints

  • Reset asserts immediately and asynchronously.
  • Reset deasserts synchronously to the destination clock.
  • Use two flip-flops in the release path.
  • Output must be active-low.
  • Must not glitch if the input reset is a runt pulse.
  • No combinational logic between the two flops.
Starter codeVerilog
1module reset_sync (2    input wire clk,3    input wire async_rst_n,4    output wire sync_rst_n5);6// TODO7endmodule