DeetCode.

Round-Robin Arbiter

Hard Verilog Arbitration Asked at AMD
Solve this problem

Implement a 4-requester round-robin arbiter that grants fairly, so no requester can be starved by a higher-numbered neighbour holding its request high.

Constraints

  • 4-bit request input, one-hot 4-bit grant output.
  • Exactly one grant asserted when any request is active.
  • Priority rotates to just after the last granted requester.
  • No grant when no request is active.
  • Must be purely synchronous with reset.
  • No combinational loops.
Starter codeVerilog
1module rr_arbiter (2    input wire clk,3    input wire rst,4    input wire [3:0] req,5    output reg [3:0] grant6);7// TODO8endmodule