DeetCode.

Serializer 8-to-1

Medium Verilog Data Flow Asked at Broadcom
Solve this problem

Convert a parallel 8-bit word into a serial bit stream with a load signal and a data-valid output, MSB first.

Constraints

  • Load captures the parallel word on a rising clock edge.
  • Shift out MSB first, one bit per clock.
  • valid is high for exactly the 8 output cycles.
  • A load during an active shift restarts the transfer.
  • Synchronous reset clears the output and valid.
  • Output must be 0 when idle.
Starter codeVerilog
1module serializer (2    input wire clk,3    input wire rst,4    input wire load,5    input wire [7:0] din,6    output reg sout,7    output reg valid8);9// TODO10endmodule