Seven-Segment Decoder with Blanking

Easy VHDL IO Asked at Samsung

Decode a 4-bit hex value to seven-segment patterns, with a ripple blanking input so leading zeros in a multi-digit display are suppressed.

Constraints

Support hex digits 0 to F.
Common-cathode: a segment lights on logic 1.
Ripple blanking input and output for cascading digits.
When rbi is low and the digit is 0, blank the display and drive rbo low.
Otherwise rbo is high.
Purely combinational.

Starter codeVHDL

1library ieee;2use ieee.std_logic_1164.all;3 4entity seg7 is5    port (6        digit : in  std_logic_vector(3 downto 0);7        rbi   : in  std_logic;8        seg   : out std_logic_vector(6 downto 0);9        rbo   : out std_logic10    );11end seg7;