Shift Register

Medium Verilog FSM
Solve this problem

Design an 8-bit shift register with synchronous reset and serial input. Shift left and output MSB.

Constraints

  • Reset clears register.
  • Rising edge triggered.
  • Serial input shifts into LSB.
  • dout = reg[7].
Starter codeVerilog
1module shreg(2    input wire clk,3    input wire rst,4    input wire din,5    output wire dout6);7// TODO8endmodule