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Shift Register Module

Medium VHDL FSM
Solve this problem

Design a shift register in VHDL with synchronous reset and serial input. The register must shift on rising clock edges and output the MSB.

Constraints

  • Width must be 8 bits.
  • Shift direction: left.
  • Reset clears register to 0.
  • Serial input shifts into LSB.
  • Output port name: dout.
Starter codeVHDL
1entity shift_reg is2  Port ( clk : in std_logic;3         rst : in std_logic;4         din : in std_logic;5         dout : out std_logic);6end shift_reg;