DeetCode.

Shift Register (VHDL)

Medium VHDL FSM
Solve this problem

Implement an 8-bit shift register in VHDL with serial input and parallel output. The register shifts left and inserts new data into bit0.

Constraints

  • Synchronous rst.
  • Rising edge triggered.
  • Parallel output is full register.
Starter codeVHDL
1entity sh8 is2  Port ( clk: in std_logic;3         rst: in std_logic;4         din: in std_logic;5         q: out std_logic_vector(7 downto 0));6end sh8;