DeetCode.

Simple ALU

Medium Verilog Architecture
Solve this problem

Create a simple ALU in Verilog supporting ADD, SUB, AND, OR operations. Use an op-code input to select the function.

Constraints

  • Inputs: a,b = 8-bit.
  • op: 2-bit (00=ADD,01=SUB,10=AND,11=OR).
  • Combinational logic.
  • Zero flag when result=0.
  • Overflow ignored.
Starter codeVerilog
1module alu(2    input wire [7:0] a,3    input wire [7:0] b,4    input wire [1:0] op,5    output reg [7:0] y,6    output reg z7);8// TODO9endmodule