SPI Master Controller
Design an SPI master supporting all four clock modes, with a configurable clock divider and a byte-at-a-time transfer interface.
Constraints
- Inputs cpol and cpha select the mode.
- 8-bit transfers, MSB first.
- sclk idles at cpol.
- Data is sampled on the edge selected by cpha and shifted on the other.
- busy asserted for the whole transfer.
- Chip select is asserted one clock before the first sclk edge.
1module spi_master (2 input wire clk,3 input wire rst,4 input wire start,5 input wire cpol,6 input wire cpha,7 input wire [7:0] tx_data,8 input wire miso,9 output reg sclk,10 output reg mosi,11 output reg cs_n,12 output reg [7:0] rx_data,13 output reg busy14);15// TODO16endmodule