SPI Slave Shift Logic

Medium VHDL Protocols Asked at NXP

Implement the shift register core of an SPI slave in mode 0, sampling MOSI on the rising SCLK edge and updating MISO on the falling edge.

Constraints

Mode 0: CPOL = 0, CPHA = 0.
Byte is received MSB first.
rx_valid pulses for one system clock when a byte completes.
Chip select deassertion must reset the bit counter.
SCLK and CS are asynchronous to the system clock and must be synchronised.
MISO must be high-impedance when CS is high.

Starter codeVHDL

1library ieee;2use ieee.std_logic_1164.all;3use ieee.numeric_std.all;4 5entity spi_slave is6    port (7        clk      : in  std_logic;8        rst      : in  std_logic;9        sclk     : in  std_logic;10        cs_n     : in  std_logic;11        mosi     : in  std_logic;12        miso     : out std_logic;13        tx_byte  : in  std_logic_vector(7 downto 0);14        rx_byte  : out std_logic_vector(7 downto 0);15        rx_valid : out std_logic16    );17end spi_slave;