DeetCode.

Synchronous FIFO with Almost-Full Flag

Hard Verilog Memory Asked at NVIDIA
Solve this problem

Build a synchronous FIFO with programmable almost-full and almost-empty thresholds so upstream logic gets back-pressure a few cycles before the buffer actually fills.

Constraints

  • Depth 16, width 8, parameterised.
  • Outputs: full, empty, almost_full, almost_empty.
  • Thresholds are module parameters.
  • A write when full and a read when empty must both be ignored.
  • Simultaneous read and write when neither full nor empty must both succeed.
  • Use a count register rather than pointer comparison for the flags.
Starter codeVerilog
1module sync_fifo #(2    parameter WIDTH = 8,3    parameter DEPTH = 16,4    parameter AF_LEVEL = 12,5    parameter AE_LEVEL = 46)(7    input wire clk,8    input wire rst,9    input wire wr_en,10    input wire rd_en,11    input wire [WIDTH-1:0] din,12    output reg [WIDTH-1:0] dout,13    output wire full,14    output wire empty,15    output wire almost_full,16    output wire almost_empty17);18// TODO19endmodule