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Synchronous ROM with Initialisation

Easy VHDL Memory Asked at Lattice Semiconductor
Solve this problem

Infer a synchronous ROM initialised from a constant array, suitable for a small waveform or character table.

Constraints

  • 16 entries of 8 bits.
  • Registered output - one cycle of read latency.
  • Contents defined as a constant array in the architecture.
  • No reset on the output register, so it infers block RAM.
  • Address wider than the depth must wrap or be masked.
  • Use numeric_std for the address conversion.
Starter codeVHDL
1library ieee;2use ieee.std_logic_1164.all;3use ieee.numeric_std.all;4 5entity sync_rom is6    port (7        clk  : in  std_logic;8        addr : in  std_logic_vector(3 downto 0);9        dout : out std_logic_vector(7 downto 0)10    );11end sync_rom;