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Testbench with Assertions

Hard VHDL Verification
Solve this problem

Develop a VHDL testbench using assertions for verifying a 4-bit adder. The testbench should stimulate inputs, verify outputs with assert statements, and report errors.

Constraints

  • DUT: sum = a + b.
  • Test multiple combinations.
  • Use assert for mismatches.
  • Stop simulation on fatal error.
  • Report pass/fail summary.
Starter codeVHDL
1entity tb is end tb;2architecture test of tb is3-- TODO4end test;